Computer Memory Performance ¶ 

In addition to the bandwidth rating of a memory module, such as PC3200 or PC2-6400, several other numbers are used to quantify memory performance. These values, known as timing parameters, quantify the response time and latency of the module. Memory is structured like a spreadsheet, with many columns and many rows, each of which contains one bit of data. Timing parameters specify the time required to perform such functions as changing the row or column and reading data. (It's not important to understand timing parameters except in a general, overall sense.)

For DDR-SDRAM and DDR2-SDRAM, memory vendors specify values, denominated in whole or fractional clock cycles, for the following four timing parameters:

CAS Latency ¶ 

CAS Latency (Column Access Strobe Latency), or tCL, specifies the number of clock cycles between the column strobe signal and when data is available on the output pins. During sequential memory accesses, the row remains activated and only the column changes, which means that the time required to change columns is critical to overall memory performance. CAS Latency, often abbreviated CL, is the most commonly quoted timing parameter and the most important memory timing parameter with respect to overall performance.

RAS to CAS Delay ¶ 

RAS to CAS Delay (Row Access Strobe to CAS Delay), or tRCD, specifies the number of clock cycles between the time a row is activated by the row strobe until the column in that row (which defines a memory cell or bit) can be read or written. When memory is accessed sequentially, the row is already active and only the column changes, so tRCD has little impact on performance. But when memory is accessed randomly, the memory controller must deactivate the old row and activate a new row, which incurs a substantial timing penalty. In that situation, a fast tRCD contributes to faster memory performance.

RAS Precharge Delay ¶ 

RAS Precharge Delay, or tRP, specifies the time required to complete one row access, deactivate that row, reactivate the next row, and begin the next row access. The time required to switch rows and select the next memory cell is therefore the sum of tRP and tRCD. For sequential memory accesses, a slow tRP has little effect; for random memory accesses, a fast tRP contributes significantly to overall memory performance.

Precharge Delay ¶ 

Precharge Delay, or tRAS, specifies the number of clock cycles between the time a row is accessed (activated) and when data can be read from that row. Once the row is activated, data can be read from that row without further overhead until the end of the row is reached, so tRAS ordinarily has little effect on overall memory performance. As with any timing parameter, setting tRAS incorrectly can reduce system stability.

These four memory timing parameters are always listed in the order given, separated by hyphens. For example, a particular PC3200 DDR-SDRAM module may list timings of 2-2-2-5, which means that module is designed to operate with timings of two clock cycles for CAS, tRCD, and tRP, and five clock cycles for tRAS. Similarly, a PC2-3200 DDR2-SDRAM module might list timings of 5-5-5-12, which means that module is designed to operate with timings of 5 clock cycles for CAS, tRCD, and tRP, and 12 clock cycles for tRAS. (Note that DDR and DDR2 timings are not directly comparable, because DDR2 operates on much shorter clock cycles.)

It is important to understand timing parameters only in that the timings you configure your system to use should not be faster than the timings supported by your memory modules. Every modern memory module contains a small chip called the SPD (Serial Presence Detect) chip, which stores the timing parameters and other characteristics of the module and reports them to the system BIOS. In the ordinary course of things, the module reports its capabilities to the BIOS and the BIOS configures the system to use appropriate settings. However, if a system is producing sporadic memory errors, you can sometimes solve the problem without replacing the memory by using BIOS Setup to specify memory timings that are more relaxed than those nominally supported by the memory modules. This step can allow you to continue using a problem system that requires memory that is unavailable or extremely expensive.

When you are adding or replacing memory in an older system, keep the following memory timing issues in mind:

  • Most motherboards can use memory of any CL timing, although some motherboards may not take advantage of the reduced latency. A few motherboards require memory with a specific CL timing. For example, a motherboard that requires CL2.5 DDR memory may not work with CL3 memory, and a motherboard that requires CL3 memory may not work properly with CL2.5 memory. This is a good reason to use the memory configurator utilities provided by Crucial and other memory makers, which take CAS latency issues into account when listing compatible memory modules.
  • Some motherboards allow mixing memory with different CL timings, although the faster memory almost always operates at the CAS latency of the slowest module installed. Some motherboards work properly with memory of different CL timings as long as all memory installed has the same CL timing, but misbehave if you install mixed modules of different CL timings. We suspect these problems are caused by minor electrical differences such as capacitance, but have never gotten a good explanation of why this is true. Although problems with mixed CL timings are unusual in our experience, we recommend not mixing CL timings for this reason.
  • Most motherboards that support different CL timings automatically configure themselves optimally based on the information reported by the memory module itself, but some require setting memory timings manually in the Chipset Configuration section of BIOS Setup. If you install "fast" modules in a system, it's worth checking BIOS Setup to make sure that the system is configured to use the faster CL timings.
  • Using conservative memory timings can increase the stability and reliability of a system at a minimal cost in reduced performance. For example, if a system has DDR CL2.5 memory installed and crashes too frequently, you can increase the stability of that system by configuring CMOS Setup to use CL3 memory timings. CL2.5 memory running as CL3 is more stable than CL2.5 memory running as CL2.5, and probably more stable than CL3 memory running as CL3. The performance hit will be so small that you won't even notice it unless you run a memory benchmark program.

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