repoman27

The Haswell iMacs support both "normal" 1.5 V DDR3 and "low voltage" 1.35 V DDR3L SODIMMs. In order to operate at the lower voltage level (which consumes less power and generates less heat), you must use all DDR3L modules, otherwise they will operate at 1.5 V since the memory bus can only be driven at a single voltage.

DSL3510L "Cactus Ridge" all around again this time. Andrew was kind enough to post links to some close-ups in the comments section of this blog post.

Out of curiosity, why do iFixit teardowns always state that the Apple SoC die is “layered over” the SDRAM die(s)? Isn’t the SDRAM always on top in a PoP configuration?

Upon further consideration, I’m pretty sure USB 2.0 never touches the Thunderbolt controllers. In a host setup, the signals are routed from the PCH to each Thunderbolt port controller. In 2-port device configurations, USB 2.0 is routed directly from the upstream port controller to the downstream port controller, unless the design requires USB 2.0 for some reason, in which case it’s routed to the upstream facing port of a hub instead.

As for JHL7440 support for USB3 hosts, the simplest way to achieve this logically is for the downstream Thunderbolt and dedicated USB ports to be connected to the downstream facing ports of a hub, with the upstream facing port of the hub connected to a 2:1 mux which can switch between the upstream Thunderbolt port and the integrated xHCI depending on the capabilities of the attached host. There is probably only a single stepping of Titan Ridge silicon, but for obvious reasons, that mux would have to be either fused off or fixed in firmware for host implementations.

The decision not to include an EHCI in Thunderbolt 3 host controllers is slightly baffling to me, but does make a modicum of sense at least in the host context. I’ve yet to determine whether the JHL7440 includes one, but if it doesn’t, then it’s a pretty ridiculous thing to leave out. You should be able to look at the USB Device Tree in System Information with a USB 2.0 device plugged into the various ports and see how it’s listed. For instance, If I connect a USB 2.0 device to the Thunderbolt 3 port of my MacBook Pro, it shows up under AppleUSBXHCISPT, which would be the Sunrise Point PCH, vs. AppleUSBXHCIAR for Alpine Ridge or AppleUSBXHCIFL1100 for Fresco Logic FL1100. There are very few two-port Titan Ridge devices in the wild where the second Thunderbolt port is actually exposed, and it may be partly due to the shenanigans involved in properly supporting USB protocols on that second port.

Yeah, but you only have a DMI 3.0 x4 uplink to the CPU, which is being oversubscribed to the tune of 2.7:1 or something like that. And the SSD controller in the T2 is perfectly capable of saturating that link all on its own.

Bluetooth module probably has a UART interface, but I can’t recall ever seeing this type of I/O bridge in previous Apple designs.

The conventional PCIe portion of slot 8 sure looks like it’s x8 both physically and electrically, yet we know that’s only billed as an x4 slot. What’s up with that? I’d really like to see better shots of the Apple I/O card.

So now you have me thinking, the C621 PCH only provides 14 USB 2.0 ports, and by my count:

2 for the Thunderbolt 3 ports on the top of the case

1 for the internal USB 3.0 Type-A port

2 for the Thunderbolt 3 ports on the Apple I/O card

2 for the USB 3.0 Type-A ports on the Apple I/O card

4 for MPX slot 1 (up to 4 Thunderbolt 3 ports)

4 for MPX slot 2 (up to 4 Thunderbolt 3 ports)

Which is one too many for the PCH, so there must be a hub or additional USB 2.0 EHCI somewhere to make that work.

I did spy a pair of TI TUSB1002A USB 3.2 10 Gbit/s dual-channel linear redrivers on the I/O card, which would be for the USB 3.0 signals routed from the PCH to the USB Type-A ports via the proprietary portion of the I/O card connector. There’s also the JHL7540, a pair of TI CD3217B or similar USB PD/Type-C port controllers, and possibly a Cirrus Logic CS42L83 audio codec on the card, but you can’t make out any of the part numbers. The audio codec probably needs a couple S2I connections to the T2 chip.

8 of the PI3EQX8904 2-lane linear redrivers are being used to redrive the 16 PCIe Gen3 lanes routed from the CPU to PCIe Slot 1 at the bottom of the board, and the other 2 are redriving the 4 PCIe Gen3 lanes headed to the built-in Thunderbolt 3 controller at the top of the case.

I’m sure the signal integrity is just fine at 8.1 GT/s, but Apple is probably the only company crazy enough to use these parts for DisplayPort seeing as they really aren’t designed for it (no included AUX or HPD support). I guess discrete DP 2x2 matrix switches aren’t really a thing, so Apple just went with what was available off-the-shelf due to this being a relatively low-volume product.

I posted my best estimation of the PCIe lane allocation in the comment thread for the other side of the logic board. Slots 2 and 4 both share 8 lanes from the PEX8796 with the proprietary side of the MPX slots by way of the 8 PI3DBS16412 muxes (6 on this side of the board, 2 on the other).

Xeon W=32xx CPUs have 64 PCIe lanes, 32 of which are connected to the 96-lane PEX8796. That leaves 32 lanes from the CPU, 64 lanes from the PEX8796, and 20 from the C621 PCH for downstream devices. Here’s my best guess as to the PCIe lane distribution:

PEX x4 dual-port Thunderbolt 3 (Intel JHL7540)

PCH x1 802.11ac Wi-Fi (Broadcom)

PEX x4 PCIe slot 8 / Apple I/O card dual-port Thunderbolt 3 (Intel JHL7540)

PEX x8 PCIe slot 7

PEX x8 PCIe slot 6

PEX x16 PCIe slot 5

PEX x8 shared + x8 PCIe slot 4 (MPX bay 2, upper slot)

PEX x8 shared MPX slot 2 (MPX bay 2, proprietary slot)

CPU x16 PCIe slot 3 (MPX bay 2, lower slot)

PEX x8 shared PCIe slot 2 (MPX bay 1, upper slot)

PEX x8 shared MPX slot 1 (MPX bay 1, proprietary slot)

CPU x16 PCIe slot 1 (MPX bay 1, lower slot)

CPU 2x x16 96-lane PCIe 3.0 switch (Broadcom PEX8796)

PCH x1 dual-UART (Pericom PI7C9X7952)

PCH x4 T2 (Apple)

PCH x4 NBASE-T 10GbE NIC 1 (Aquantia AQC107)

PCH x4 NBASE-T 10GbE NIC 2 (Aquantia AQC107)