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Edit by Miroslav Djuric:

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[* black] The raised mesa-looking shapes in the right mostmagnified cross-section view (larger magnificationsecond image) are the transistors' structures, and the little pegs running between them are the actually the contacts between layers.
[* black] The raised mesa-looking shapes in the right mostmagnified cross-section view (larger magnificationsecond image) are the transistors' structures, and the little pegs running between them are the actually the contacts between layers.
[* black] We can't help but think that the transistor layout looks a lot like a Roman [http://upload.wikimedia.org/wikipedia/commons/thumb/d/d8/Pont_du_Gard_Oct_2007.jpg/300px-Pont_du_Gard_Oct_2007.jpg|aqueduct].
[* red] This very thin line confirms that this is a 32 nm HKMG (Hi-K metal gate) process.
[* black] The A6's 32 HKMG process is the same as the one utilized in the [guide|8293|Apple TV 3rd Generation|stepid=33185] (APL2498 on Chipworks).
[* black] In an [http://en.wikipedia.org/wiki/FET|FET (Field Effect Transistor)], K is the dielectric constant of the layer between the gate electrode and the silicon. This is a physical parameter of the material which helps control the turn-on voltage of the transistor