Changes to revision 142206:

Edit by Walter Galan:

Accepted by Walter Galan

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[* black] The raised mesa-looking shapes in the cross-section view are the transistors' structures, and the little pegs running between them are the actually the contacts between layers.
[* black] We can't help but think that the transistor layout looks a lot like a Roman [http://upload.wikimedia.org/wikipedia/commons/thumb/d/d8/Pont_du_Gard_Oct_2007.jpg/300px-Pont_du_Gard_Oct_2007.jpg|aquaduct].
[* red] This very thin line confirms that this is a 32nm [link|http://en.wikipedia.org/wiki/High-k_dielectric|HKMG] (Hi-K metal gate) process.
[* black] The A6's 32 HKMG process is the same as the one in the Apple[link|http://www.ifixit.com/Teardown/Apple-TV-3rd-Generation-Teardown/8293/1#s33185|Apple TV 3rd Generation] (APL2498 on Chipworks).
[* black] The A6's 32 HKMG process is the same as the one in the Apple[link|http://www.ifixit.com/Teardown/Apple-TV-3rd-Generation-Teardown/8293/1#s33185|Apple TV 3rd Generation] (APL2498 on Chipworks).
[* black] In an [http://en.wikipedia.org/wiki/FET|FET (Field Effect Transistor)], K is a physical parameter of the device that depends on the doping levels of the silicon and the size of the transistor. The gate is the control pin on an FET.