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Edit by Andrew Optimus Goldberg:

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[* black] The raised mesa-looking shapes in the cross-section view are the transistors' structures, and the little pegs running between them are the actually the contacts between layers.
[* black] We can't help but think that the transistor layout looks a lot like a Roman [http://upload.wikimedia.org/wikipedia/commons/thumb/d/d8/Pont_du_Gard_Oct_2007.jpg/300px-Pont_du_Gard_Oct_2007.jpg|aquaduct].
[* red] This very thin line confirms that this is the 32nm HKMG (Hi-K metal gate) process.
[* black] The A6's 32 HKmg process is the same as used in Apple TV (APL2498 on Chipworks).
[* black] In aan [http://en.wikipedia.org/wiki/FET|FET (Field Effect Transistor)], K is a physical parameter of the device that depends on the doping levels of the silicon and the size of the transistor. The gate is the control pin on an FET.
[* black] In aan [http://en.wikipedia.org/wiki/FET|FET (Field Effect Transistor)], K is a physical parameter of the device that depends on the doping levels of the silicon and the size of the transistor. The gate is the control pin on an FET.